1. Field of the Invention
The present invention relates to a potential detecting circuit, and more particularly to a potential detecting circuit for detecting a potential which is similar to the power source potential of a CMOS LSI, and a potential which is much higher than the reference potential or the power source potential of the CMOS LSI.
2. Description of the Related Art
In an LSI with a nonvolatile memory, for example an EPROM, it is required that a write mode be changed to a read mode, and vice versa. To operate the LSI in the write mode, an externally applied voltage V.sub.pp, which is much higher than the LSI power source V.sub.DD potential, is required.
FIG. 1 shows a prior art potential detecting circuit. In this circuit, an input terminal IN for receiving an input potential VIN is grounded through PMOS transistors P1 and P2 and an NMOS transistor N1. A potential detection signal is derived from an output terminal OUT1, through an inverter consisting of two pairs of MOS transistors P3 and N3, and P4 and N4.
The high breakdown voltage transistor is different from the transistor of the V.sub.DD system in the following respects:
1) The high breakdown voltage transistor has an LDD (lightly doped drain) structure.
2) The high breakdown voltage transistor has a thick gate oxide film.
In FIG. 1, the MOS transistors of the LDD structure are indicated by small circles attached to the drains.
Let us consider two different operations of the prior art potential detecting circuit shown in FIG. 1, when the input potential of the circuit is equal to an LSI power source, high potential V.sub.pp, e.g., 20 V, which is much higher than an LSI power source, low potential V.sub.DD, e.g., 5 V, and when the input potential is equal to the power source potential V.sub.DD.
a) When the high potential V.sub.pp (20 V) is applied to the input terminal IN, a potential at node 5 is lower than the potential V.sub.pp by the amount of the threshold voltage V.sub.THp1 of the PMOS transistor P1. If the potential at node 5 is higher than a sum of the threshold voltage V.sub.THp2 of the PMOS transistor P2 and the gate potential V.sub.DD, the PMOS transistor P2 is turned on. Under this condition, a current flows from the input terminal IN to the ground point G through the PMOS transistors P1 and P2 and the NMOS transistor N1. The potential at node 6 progressively rises by a ratio of the sum of the ON-resistance of the PMOS transistors P1 and P2 to the ON resistance of the NMOS transistor N1.
i) When the potential at node 6 is higher than the threshold voltage of the inverter including the MOS transistors P3 and N3, a potential at the V.sub.DD level is output from the output terminal OUT1. ii) When the former is lower than the latter. A ground level potential is output from the output terminal OUT1.
b) When a potential V.sub.DD equal to or lower than the potential V.sub.pp is applied to the input terminal IN, the potential at node 5 is lower than a sum of the threshold voltage V.sub.THZ of the PMOS transistor P2 and the gate potential V.sub.DD. Therefore, the transistor P2 remains off while the transistor N1 remains on. Accordingly, a ground level potential is output from the output terminal OUT1.
In this way, the potential detecting circuit can detect the input potential V.sub.IN, the high potential V.sub.pp, or the low potential V.sub.DD. The potential detecting circuit is characterized in that, even when a potential between the ground level and the V.sub.DD level is applied to the input terminal, the PMOS transistor P2 is turned off, and hence no DC path is formed. It is also characterized in that the drains of the transistors P3 and N3 are of the LDD structure type and can withstand a high potential applied to the gates of those transistors.
To assemble the circuit, including the high break-down voltage PMOS transistor P2 and the like as shown in FIG. 1, into an LSI chip which does not use high breakdown voltage PMOS transistors, another type of transistors must be used. This means that the number of manufacturing process steps must increase. In this regard, it should be noted that to manufacture an LSI containing elements such as E.sup.2 PROM, polysilicon electrodes for the V.sub.DD system and those for the high breakdown voltage cells are separately formed. In this case, the following additional three steps are performed in the photo etching process:
a) To implant ions into the channels of high breakdown voltage PMOS transistors,
b) To form the LDD structure of high breakdown voltage NMOS transistors by using a mask, and
c) To form the LDD structure of high breakdown voltage PMOS transistors by using a mask.
It is evident that the increased number of process steps leads to an increase in the manufacturing cost and manufacturing time.